`include "../rtl/top_risc.v"
`include "../rtl/rom.v"
module open_soc(
    input wire clk,
    input wire rst_n
);

//open_risc to rom
wire [31:0] open_risc_inst_addr_o;

//rom to open_risc
wire [31:0] rom_inst_o;


top_risc u_top_risc_open_soc_1(
    .clk    ( clk    ),
    .rst_n  ( rst_n  ),
    .inst_i ( rom_inst_o ),
    .inst_addr_o  ( open_risc_inst_addr_o  )
);

rom u_rom_open_soc_1(
    .inst_addr_i ( open_risc_inst_addr_o ),
    .inst_o      ( rom_inst_o      )
);


endmodule